1. Field of the Invention
The present invention relates to a method for the addressing of an integrated circuit memory and to a device which can be used to implement the method. It concerns, more particularly, a method for the addressing of redundant elements of the memory.
2. Description of the Prior Art
An integrated circuit memory usually comprises row memory elements, addressable by row addresses, and column memory elements, addressable by column addresses. The memory also comprises redundant memory elements designed to replace faulty elements of the memory. These redundant elements consist of row and column memory elements, the rows being also addressable by the row addresses and the columns by the column addresses.
When an element in the memory proves to be faulty, following a test of this memory, the address of this element is stored by a group of fuses in which certain fuses are blown, so that the state of each blown fuse represents the address of the detected faulty element. The use of a battery of fuses for each faulty element is quite natural and usual. It is also natural and usual to use separate groups for row elements and column elements. The current trend is towards the use of an increasing number of redundant elements, so that the number of fuse groups is increasing. This increase is contributing, firstly, to greater bulk and, secondly, to greater risks of failure.
It is an object of the invention to reduce the space occupied by the groups used for routing towards the redundant elements, by using only one battery for a row/column pair of the memory and by indicating, at the end of each row and column test, the nature of the routing operation through the blowing of a fuse. Consequently, the fact that a fuse is blown or not makes it possible to ascertain whether the faulty element is a row element or a column element. This permits directing the routing towards a row redundant element or towards a column redundant element.